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The IEEE 1500 standard for embedded core test, approved in 2005, defines a scalable and reusable wrapper architecture that allows the testing of, and access to, embedded cores within a system on chip (SoC). The wrapper is controlled using a Wrapper Instruction Register (WIR), and has serial and parallel ports for test access mechanisms (TAMs) to deliver test vectors to the cores under test. In this study, the authors consider two implementation challenges that are outside the IEEE 1500 standard: how multiple WIRs within a SoC are controlled and accessed and also the TAM architecture. The authors present novel solutions to both challenges in the form of a test controller to interface with the embedded IEEE 1500 structures and also a TAM architecture that reuses the physical interconnections of an on-chip system bus. The test controller facilitates concurrent test of multiple IEEE 1500 wrapped cores in an SoC through the IEEE 1149.1 test access port (TAP). Reusing the physical interconnections of the system bus as a TAM is not dependent on the system bus protocol or functionality.