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The lack of self-alignment between the gate and the source/drain electrodes is significant problem for printed transistors, since alignment is typically limited by the layer-to-layer registration capabilities of the printer. This in turn necessitates the use of design rules specifying large gate-to-source/drain overlaps, resulting in degraded switching speed due to the large overall capacitance . Here, for the first time, we demonstrate the realization of self-aligned transistors in a fully inkjet-printed process, without the need for any lithography or vacuum processing. With self-aligned printing of the source/drain to the gate, we achieve a minimum overlap of 0.78um between the gate the source/drain, contrasted to the >10um typically required in conventional printed transistors. As a result, the cut-off frequency of the printed transistor is significantly enhanced since parasitic overlap capacitances are minimized. Moreover, variations of the channel length can be reduced since the channel length is now defined by self-alignment. In contrast to previous reports on self-aligned printed devices , we achieve self-alignment in a fully-printed process without using any lithographic steps.