A signal-swing suppressing strategy for power and layout area savings using time-multiplexed differential data-transfer scheme

This paper presents a signal-swing suppression strategy which uses a time-multiplexed differential data-transfer (TMD) scheme combined with a data-transition detector (DTD) circuit, featuring shared complementary wires, which are originally allocated to adjacent signal bits, respectively. TMD can be exploited to reduce the signal voltage-swing and to realize a charge-recycling bus (CRB) architecture. This enables a dramatic power reduction without the throughput-loss due to time-multiplexing, while maintaining the same number of signal wires compared to a single signal line (SSL) scheme. This is because the differential transfer scheme inherently has a more capability in terms of throughput and noise tolerance compared to SSL. To demonstrate the effectiveness of TMD with DTD and TMD with CRB (TM-CRB), power consumption comparisons were made between SSL, the parallel architecture, TMD with DTD, and TM-CRB. For all measurements, the same throughput conditions were used based on the simulated and measured data of the 0.5 /spl mu/m CMOS devices. This paper presents why TM-CRB can reduce the power dissipation on heavily loaded bus lines to less than 1/31 and 1/8, with bus activity of 100% and 25%, respectively, while maintaining the same number of signal wires, compared to SSL.