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A low-power, ultra-low capacitance BICMOS process applied to a 2 GHz low-noise amplifier

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6 Author(s)
van der Wel, W. ; Philips Semicond., Nijmegen, Netherlands ; Koster, Ronald ; Jansen, S.C.L. ; Ahlrichs, F.W.
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A BICMOS process is presented that includes an ultra-low capacitance NPN bipolar transistor (PRET) together with conventional 10 GHz single-poly NPN and MOS devices. Isolation is done using shallow (STI) and deep trenches. The mechanism of capacitance reduction by STI is discussed. The PRET concept, with a 0.2 μm-wide emitter is shown to yield record low capacitances (emitter/base: 1.5 fF, collector/base: 1 fF) combined with high-frequency capability (the cut-off frequency is 14 GHz). This concept is demonstrated in a 2 GHz low-noise amplifier. Proper functioning is obtained at a 3 times lower power consumption than previously reported in literature

Published in:

Electron Devices, IEEE Transactions on  (Volume:43 ,  Issue: 9 )

Date of Publication:

Sep 1996

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