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Ten-bit 100 MS/s 24.2 mW 0.8 mm2 0.18 μm CMOS pipeline ADC based on maximal circuit sharing schemes

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5 Author(s)
K. -H. Lee ; Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea ; S. -W. Lee ; Y. -J. Kim ; K. -S. Kim
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A ten-bit (10b) 100 MS/s 0.18 ??m CMOS three-step pipeline ADC with various circuit sharing techniques is described. Two MDACs share a single two-stage low-power switched amplifier without MOS series switches and memory effects as observed in conventional shared op-amps. All three flash ADCs use only one resistor ladder rather than three for reference voltages while the second and third flash ADCs share pre-amps for area and power reduction. The prototype ADC with an active die area of 0.80 mm shows a maximum SNDR and SFDR of 54.2 and 68.8 dB, respectively, and consumes 24.2 mW at 1.8 V and 100 MS/s.

Published in:

Electronics Letters  (Volume:45 ,  Issue: 25 )