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Low-glitch, high-speed charge-pump circuit for spur minimisation

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2 Author(s)
I. -C. Hwang ; Kangwon National University, Chuncheon, Korea ; S. -G. Bae

For spur reduction in RF frequency synthesisers, a simple and effective charge-pump circuit is proposed. A prototype frequency synthesiser fabricated on a 0.13 ??m CMOS process, achieves -71.32 dBc at 8.184 MHz offset from a 1.571 GHz carrier with just a second-order loop filter. When the spur level is converted to the input phase error of the PFD, it equals 0.0026 rad.

Published in:

Electronics Letters  (Volume:45 ,  Issue: 25 )