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In-circuit hot-carrier model and its application to inverter chain optimization

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1 Author(s)
Horiuchi, T. ; ULSI Device Dev. Labs., NEC Corp., Kangawa, Japan

An analytical in-circuit device lifetime model and design methodology for minimizing hot-carrier effects in an inverter chain are presented. Based on the model, in-circuit device lifetime, τAC , for hot-carrier induced degradation is given by τAC DC/R, R≡√π/2√Vcc/b√(T rise.Tfall)/Tc where τDC is the device lifetime under a DC test, Trise and Tfall are the rise time for input and fall time for output, TC is cycle time and b is a constant. The model also shows that minimizing circuit delay in the inverter chain maximizes hot-carrier reliability

Published in:

Electron Devices, IEEE Transactions on  (Volume:43 ,  Issue: 9 )

Date of Publication:

Sep 1996

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