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Logarithmic number system (LNS) arithmetic, which represents real numbers by their logarithm in base two, offers inexpensive, error-free multiplication and division, as well as better error characteristics than floating point (FP) arithmetic, but difficult addition/subtraction. While most DSPs use fixed-point arithmetic, floating point would be attractive if it could be achieved at low cost. This paper describes an LNS core that achieves better area than contemporary FP processors. The new approach uses a function interpolator using stored function values, represented in a new interleaved ROM architecture.