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This paper demonstrates a digitally testable second-order Σ - Δ modulator. The modulator under test (MUT) employs the decorrelating design-for-digital-testability (D3T) scheme to provide two operation modes: the normal mode and the digital test mode. In the digital test mode, the input switched-capacitor network of the D3T modulator is reconfigured as two sub-digital-to-charge converters (sub-DCCs). Each of the sub-DCCs accepts a Σ - Δ modulated bit-stream as its test stimulus. By repetitively inputting the DCCs with the same Σ - Δ modulated bit-stream but with different delays, the DCCs incorporates with the integrator to generate the analog stimulus in the digital test mode. The analog stimulus is analogous to the result of filtering the bit-stream with a two-nonzero-term FIR decorrelating term. Consequently, the D3T MUT suffers less from the undesired shaped noise of the digital stimuli, and achieves better digital test accuracy. Measurement results show that the digital tests present a peak signal-to-noise-and-distortion ratio (SNDR) of 80.1 dB at an oversampling ratio of 128. The SNDR results of the digital tests differ from their conventional analog counterparts by no more than 2 dB except for the -3.2 dBFS test. The analog hardware overhead of the D3T MUT only consists of 13 switches.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:19 , Issue: 3 )
Date of Publication: March 2011