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Implementation of a high-speed parallel Turbo decoder for 3GPP LTE terminals

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4 Author(s)
Di Wu ; Dept. of Electr. Eng., Linkoping Univ., Linkoping, Sweden ; Asghar, R. ; Yulin Huang ; Liu, D.

This paper presents a parameterized parallel Turbo decoder for 3GPP LTE terminals. To support the high peak data-rate defined in the forthcoming 3GPP LTE standard, turbo decoder with a throughout beyond 150 Mbit/s is needed as a key component of the radio baseband chip. By exploiting the tradeoff of precision, speed and area consumption, a turbo decoder with eight parallel SISO units is implemented to meet the throughput requirement. The turbo decoder is synthesized, placed and routed using 65 nm CMOS technology. It achieves a throughput of 152 Mbit/s and occupies an area of 0.7 mm2 with estimated power consumption being 650 mW.

Published in:

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Date of Conference:

20-23 Oct. 2009