By Topic

A low power high date rate ASK IF receiver

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Xiaoman Wang ; Institute of Microelectronics, Tsinghua University, Beijing 100084, China ; Baoyong Chi ; Zhihua Wang

A low power high data rate ASK IF receiver is proposed. It consists of one digital-control AGC loop and an ASK detector. By utilizing the scrambler concept in the digital communication systems, the gain of PGA in the AGC loop is adjusted discretely by a gain control block to eliminate the multi-digit A/D converter. The ASK IF receiver has been implemented in 0.18 ¿m CMOS and the overall power consumption is 2.175 mW with a supply voltage of 1.8V. The operating frequency is 10M, and the data rate is 2 Mbps. The amplitude of detectable input signal can range from 5 ¿V to 900 mV.

Published in:

2009 IEEE 8th International Conference on ASIC

Date of Conference:

20-23 Oct. 2009