A low power high date rate ASK IF receiver

A low power high data rate ASK IF receiver is proposed. It consists of one digital-control AGC loop and an ASK detector. By utilizing the scrambler concept in the digital communication systems, the gain of PGA in the AGC loop is adjusted discretely by a gain control block to eliminate the multi-digit A/D converter. The ASK IF receiver has been implemented in 0.18 ¿m CMOS and the overall power consumption is 2.175 mW with a supply voltage of 1.8V. The operating frequency is 10M, and the data rate is 2 Mbps. The amplitude of detectable input signal can range from 5 ¿V to 900 mV.