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DReNoC: A dynamically reconfigurable computing system based on network-on-chip

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5 Author(s)
Ying-Chun Chen ; Institute of VLSI Design, Hefei University of Technology, China ; Gao-Ming Du ; Luo-Feng Geng ; Duo-Li Zhang
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A dynamically reconfigurable computing system based on network-on-chip (DReNoC) is proposed, which consists of computing nodes and communication nodes. The computing node is a complete coarse-grained dynamically reconfigurable SoC named DReSoC. And the DReSoCs communicate with each other through on chip network routers. The proposed DReNoC has been implemented on the ALTERA STRATIX II EP2S180 DSP development board with 48063 Combinational ALUTs and 26211 logic registers. Experimental result of 8?8 matrix sequential matrix multiplications showed that, compared with a single-core system-on-chip (SoC) based on the standard Nios II processor, the speed-up ratio can reach 124.91.

Published in:

2009 IEEE 8th International Conference on ASIC

Date of Conference:

20-23 Oct. 2009