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VLSI architecture of a low complexity face detection algorithm for real-time video encoding

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4 Author(s)
Tianruo Zhang ; Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Fukuoka, 808-0135 Japan ; Minghui Wang ; Chen Liu ; Satoshi Goto

Combining video encoder and content analyzer to improve the encoding efficiency by content-aware algorithms is very challenging now. For the aiming application of low cost hardware real-time encoder with face detection for videophone, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification process and can be combined with a H.264 encoder by MB level pipeline architecture. 97.91% MBs in faces can be detected. VLSI architecture of proposed face detection algorithm is designed and an area of 4.3k gates is achieved. Power consumption is only 1.45mW at 100MHz. The detection speed achieves 1315fps in CIF sequences.

Published in:

2009 IEEE 8th International Conference on ASIC

Date of Conference:

20-23 Oct. 2009