By Topic

VLSI architecture of a low complexity face detection algorithm for real-time video encoding

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Tianruo Zhang ; Grad. Sch. of Inf., Production & Syst., Waseda Univ., Fukuoka, Japan ; Minghui Wang ; Chen Liu ; Goto, S.

Combining video encoder and content analyzer to improve the encoding efficiency by content-aware algorithms is very challenging now. For the aiming application of low cost hardware real-time encoder with face detection for videophone, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification process and can be combined with a H.264 encoder by MB level pipeline architecture. 97.91% MBs in faces can be detected. VLSI architecture of proposed face detection algorithm is designed and an area of 4.3k gates is achieved. Power consumption is only 1.45mW at 100MHz. The detection speed achieves 1315fps in CIF sequences.

Published in:

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Date of Conference:

20-23 Oct. 2009