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Motion compensation is the most critical part for the performance of H.264 decoder. Through fully analysis of the interpolation algorithm, a symmetry characteristic in the algorithm has drawn our attention. Based on a precise deduction, a new VLSI architecture for motion compensation lum interpolation is presented in this paper. This architecture is based on separated 1-D approach and reuses the horizontal half-sample interpolation 6-tap FIRs and the horizontal vertical half-sample interpolation 6-tap FIRs. Experiment results shows that compared with arithmetic adopting separated 1-D approach referenced, the proposed arithmetic can save 5 6-tap FIRs and 6 eight-bit registers. A H.264 decoder adopting the proposed approch can achieve real-time decoding 30 fps baseline H.264/AVC video with 1080HD resolutions at a clock speed of 100 MHz.