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A parallel and dynamic reconfigurable hardware architecture of MICKEY algorithm is proposed in this paper, which can satisfy the different characteristics of MICKEY-80, MICKEY-128 and MICKEY-128 2.0 algorithms. The three algorithms are exactly the same in design principle, so according to different reconfigurable parameters, they can be implemented in one chip. As to different parallel methods, detailed comparison and analysis are performed. The design has been realized using Altera's FPGA. Synthesis, placement and routing of parallel and reconfigurable design have accomplished on 0.18 Â¿m CMOS process. The result proves the maximum throughput can achieve 1915.8 Mbps.