By Topic

Research and implementation of parallel and reconfigurable MICKEY algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Li Miao ; Zhengzhou Inf. Coll., Zhengzhou, China ; Xu Jinfu ; Dai Zibin ; Yang Xiaohui
more authors

A parallel and dynamic reconfigurable hardware architecture of MICKEY algorithm is proposed in this paper, which can satisfy the different characteristics of MICKEY-80, MICKEY-128 and MICKEY-128 2.0 algorithms. The three algorithms are exactly the same in design principle, so according to different reconfigurable parameters, they can be implemented in one chip. As to different parallel methods, detailed comparison and analysis are performed. The design has been realized using Altera's FPGA. Synthesis, placement and routing of parallel and reconfigurable design have accomplished on 0.18 ¿m CMOS process. The result proves the maximum throughput can achieve 1915.8 Mbps.

Published in:

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Date of Conference:

20-23 Oct. 2009