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High performance and low latency mapping for neural network into network on chip architecture

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4 Author(s)
Yiping Dong ; Graduate School of Information, Production and Systems, Waseda University, Japan ; Yang Wang ; Zhen Lin ; Takahiro Watanabe

Various hardware implementations of neural networks have been studied well in recent years. We have already proposed a hardware implementation method for neural network with a network on chip (NoC) architecture. A mapping of a neural network on NoC should be tuned to achieve high performance whenever neural network application is changed, so that different mapping methods are needed every time and tedious or burdensome works are required. In this paper, we propose a general mapping strategy based on three rules. The mapping method with this strategy can implement different neural networks applications with NoC architecture. The simulation results show that the proposed method makes the system low latency and high performance.

Published in:

2009 IEEE 8th International Conference on ASIC

Date of Conference:

20-23 Oct. 2009