Skip to Main Content
This paper describes a low power, low voltage sigma-delta analog to digital converter which consists of a sigma-delta modulator (SDM) and a decimation digital filter. A power efficient class AB OP-AMP, derived from inverter-like amplifier circuit, is proposed and a modified digital filter structure is employed for low frequency operation. Designed in a 0.18-μm CMOS technology, the overall SD-ADC is able to achieve an ENOB of 13.4 bit, a dynamic range of 88.6 dB and a peak SNR of 82.7 dB. The total power consumption of the ADC is 32 μW.