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A mixed-signal calibration technology for the pipeline A/D converter

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5 Author(s)
Shang-Quan Liang ; Institute of VLSI design, Hefei University of Technology, Hefei, China ; Yong-Sheng Yin ; Hong-Hui Deng ; Xiao-Lei Wang
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A mixed-signal calibration architecture and algorithm based upon 14bits 1.5b/s pipeline A/D converter is proposed. The mixed-signal calibration algorithm consists of analog domain calibration and digital domain calibration. The analog-domain calibration algorithm adopts the level shifting technology to shift the input signal to lower voltage range. The digital output is reconstructed in the digital-domain after analog-to-digital conversion. The digital-domain calibration algorithm adopts code-by-code compensation technique and constructs a linear equation by the method of awaiting determined coefficients. An error calibration look-up table is acquired through the digital-domain calibration. A behavioral-level model of 14 bits 1.5 b/s pipeline ADC with mixed-signal calibration algorithm is established. The results show that the proposed calibration architecture and algorithm can effectively calibrate errors. The INL and DNL are reduced within ±0.5LSB. The SNDR is improved from 30.8 dB to 84.5 dB, and the ENOB is arrived to 13.74 bits.

Published in:

2009 IEEE 8th International Conference on ASIC

Date of Conference:

20-23 Oct. 2009