By Topic

A 1.8V CMOS polar transmitter front-end for 900MHz EDGE system

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Ran Ren ; CARFIC (Center for Analog/RF Integrated Circuits) Lab., Shanghai Jiao Tong Univ., Shanghai, China ; Taotao Yan ; Peichen Jiang ; Hao Hu
more authors

A 900 MHz low-noise high-linearity polar transmitter front-end for EDGE system is presented, including a multiplier as well as a driver amplifier. The whole circuit is implemented in IBM 0.18 ¿m CMOS process. The multiplier and DA provide output power ranging from -30 dBm to 4.5 dBm, an ACPR of -63 dBc at 400 KHz offset and an output noise of -167 dBm/Hz at 20 MHz offset. The spurious around 2nd and 3rd harmonics are -46 dBc and -39 dBc respectively. The carrier suppression is -45dBc. The whole circuit consumes 23~56 mA from a 1.8 V supply voltage according to different gain levels.

Published in:

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Date of Conference:

20-23 Oct. 2009