All digital wireless transceiver using modified BPSK and 2/3 sub-sampling technique

In this paper an all digital wireless transceiver is presented, with a proposed technique for data recovery. Communication is carried out on carrier frequency of 100 MHz with a local clock of 2/3 carrier frequency on the receiver side used to sub-sample incoming wireless signal and understand transmitted data. A modified BPSK is employed, which stretches periods of phase change to enable data recovery in our all digital circuit without clock recovery. The transceiver is implemented and tested on FPGA connected to coils to perform actual short range wireless communication. Our design uses no analog components and our target is to consume as low power as possible, which makes it suitable for low power applications like wireless image sensor nodes.