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Multi-gate-length (MGL) and dual-gate-length (DGL) biasing techniques are investigated for timing constraint-aware active mode leakage power reduction of VLSI circuits. Key design and technology characteristics essential for leakage reduction are identified and utilized to carry out a Monte-Carlo-based study to benchmark MGL against DGL over different design styles and various technologies. Extensive results indicate that MGL offers generally modest to small advantage over DGL. Novel analytical models have been developed to describe leakage reduction capability of DGL/MGL and reveal its dependences on key design/technology characteristics to quantitatively assess the cost-benefit trade-off of implementing DGL/MGL.