By Topic

The design of a sub-nanojoule asynchronous 8051 with interface to external commercial memory

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Chao Xue ; National University of Singapore ; Xiang Cheng ; Yang Guo ; Yong Lian

In this paper, we present the design of an asynchronous 8051 microcontroller with interface to external commercial memory. The design consists of an asynchronous core implemented using dual-rail four-phase protocol, a 128 byte internal asynchronous RAM and other synchronous peripherals including interrupts, timers and serial port. The asynchronous core contains all standard 8051 instructions except for multiplication and division. The interface to external commercial ROM and SRAM is controlled by two internal counters with adjustable overflow values to accommodate potentially variable clock source and external memory access time. An acknowledge signal is generated once the counter overflows which indicates the completion of a read/write operation. The chip is implemented using Austria Micro Systems (AMS) 0.35¿m technology. It is able to operate at 0.22 MIPS and consume 141pJ/Instruction at 1.0V supply. Another two-stage pipelined version designed later operates at 0.3MIPS and consumes 180pJ/Instruction at the same supply.

Published in:

2009 IEEE 8th International Conference on ASIC

Date of Conference:

20-23 Oct. 2009