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In this paper, we have proposed a design and implementation of an AMBA based advanced DMA controller. The DMAC has 8 channels which support hardware and software triggers, linking operation and channel chaining transfer and provides three dimensions transmission by parameter sets so as to perform data block moving, data sorting and subframe extraction of various data structures. Channel arbitration mechanism adopts hardware priority combined with weighted priority rotational algorithm. Moreover the DMAC supports incrementing and wrapping addressing modes and completes data transfer which the data width of read and write is different by asymmetric asynchronous FIFO. Furthermore the DMAC adopts dual-clock domain design so as to decrease the power consumption. The DMAC has the function of APB Bridge, and achieves AHB bus and APB bus to run in parallel. And the DMAC could adopt buffer and non-buffer data transfer mode according to the speed of equipments. With 0.18 um library technology of SMIC, a working frequency of 408 MHZ is achieved. Experimental results show that the DMAC has better performance than traditional DMAC and DMA PL081.