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A study and design of CMOS H-Tree clock distribution network in system-on-chip

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3 Author(s)
Wei-Khee Loo ; Fac. of Eng., Multimedia Univ., Cyberjaya, Malaysia ; Kok-Siang Tan ; Ying-Khai Teh

A design of a low skew clock distribution network is presented based on the TSMC 0.18 ¿m CMOS technology. This work first investigated various aspects in designing a clock distribution network. After that, the design methodology for the chosen H-Tree clock network topology is presented. A series of design performance analyses such as clock delay, skew, rise and fall time, supply voltage and temperature variations and power consumption were compared for both pre-layout and post-layout simulation results. Pre-layout and post-layout simulation results validated the 3-segment ¿-model. The clock network designed is able to operate up to maximum clock speed of 1.1 GHz for a 1×1 mm2 chip with zero skew.

Published in:

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Date of Conference:

20-23 Oct. 2009