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A design of a low skew clock distribution network is presented based on the TSMC 0.18 Â¿m CMOS technology. This work first investigated various aspects in designing a clock distribution network. After that, the design methodology for the chosen H-Tree clock network topology is presented. A series of design performance analyses such as clock delay, skew, rise and fall time, supply voltage and temperature variations and power consumption were compared for both pre-layout and post-layout simulation results. Pre-layout and post-layout simulation results validated the 3-segment Â¿-model. The clock network designed is able to operate up to maximum clock speed of 1.1 GHz for a 1Ã1 mm2 chip with zero skew.