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Design of SoC verification platform based on VMM methodology

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5 Author(s)
Lu Kong ; VLSI & Syst. Lab., Beijing Univ. of Technol., Beijing, China ; Wu-Chen Wu ; Yong He ; Ming He
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A VMM-based verification platform has been implemented and applied to Yak SoC in this paper. The whole verification environment uses the SystemVerilog language, and the simulation tool adopted is Synopsys VCS-MX200606. The verification IP and SystemVerilog assertions help to heighten the performance of the platform. The verification results indicate that design errors of timing and anti-protocols have been exactly checked out with 100% verification coverage. The proposed platform, possessing fine configurability, flexibility and high performance, can be reused in similar verifications of other design.

Published in:

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Date of Conference:

20-23 Oct. 2009