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Direct digital frequency synthesizer(DDS) is a new technology for frequency synthesis. This paper describers the implementation of a direct digital frequency employs a new architecture in 0.35 Â¿m CMOS technology. The first rotation implementer by using a CORDIC realized in pipeline and carry-save arithmetic. The directions of the CORDIC rotations are computed in parallel by using a little lookup table, for the first rotation. In order to reduce the circuit latency and increase the speed, the final rotation is multiplier-based, employing CMOS-DPL logic. The final circuit experiment results show the power dissipation as low as 1.44mW/MHz and the maximum clock frequency 200 MHZ.