A flexible parameter mismatch sensitivity analysis for VLSI design

A sensitivity analysis technique, which is based on Placket Burman Matrix for experimental design is proposed in this report. The response is obtained by simulating an op amp using a SPICE circuit simulator. The response is then used to study the effect of transistor parameter mismatch on circuit performance. This technique models the parameter mismatch effect by creating an addition parameter term. The amount of deviation is a function of fabrication process, bias condition and device type (PMOS or NMOS). The integration method is illustrated in this paper. The modeling method allows parameter variation information to be shared by different nominal device models. The methodology discussed here can be applied to any new circuit topology; hence it is flexible. In addition, the sensitivity analysis provides a quantitative measure while keeping the number of required simulation to the minimum. Therefore, it is readily extended to design automation environment. A unity gain buffer CMOS op amp is used as an example to illustrate the concepts behind this technique.