By Topic

High Resolution FPGA DPWM Based on Variable Clock Phase Shifting

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
de Castro, A. ; Escuela Politec. Super., Univ. Autonoma de Madrid, Madrid, Spain ; Todorovich, E.

This letter proposes a very high resolution digital pulsewidth modulator (DPWM) architecture that takes advantage of a field-programmable gate array (FPGA) advanced clock management capability - the fine phase shifting of the clock. This feature is available in almost every FPGA nowadays, thus allowing very small and programmable delays between the input and output clocks. An original use of this fine phase shifting pushes the limits of DPWM resolution. The experimental results show a time resolution of 19.5 ps in a Virtex-5 FPGA.

Published in:

Power Electronics, IEEE Transactions on  (Volume:25 ,  Issue: 5 )