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Self-aligned fabrication of 10 nm wide asymmetric trenches for Si/SiGe heterojunction tunneling field effect transistors using nanoimprint lithography, shadow evaporation, and etching

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2 Author(s)
Chao Wang ; Department of Electrical Engineering, NanoStructure Laboratory, Princeton University, New Jersey 08544 ; Chou, S.Y.

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Fabrication of an asymmetric source/drain structure is important to heterojunction tunneling transistors but is extremely difficult to achieve reliably due to the stringent requirement of nanometer overlay alignment. Here the authors propose and demonstrate a simple self-aligned asymmetric nanotrench fabrication method, which has achieved a 10 nm wide (35 nm deep) trench in source region with an alignment accuracy better than 3 nm. The method is based on asymmetric shadow evaporation of the metal with the gate as a mask, creating an area uncovered by the metal only in the source but not in the drain, and a subsequent reactive ion etching with the evaporated metal as the etching mask. The accuracy of this method was found experimentally and theoretically to be within 5 nm.

Published in:

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures  (Volume:27 ,  Issue: 6 )