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Today's computer systems have become unbelievably complex. Nowadays register-level design is an overwhelming task, especially in the embedded system area where the time-to-market is very short. Platform based design shifts the challenge on how to tune parametric platforms to achieve the best performance at the smallest cost. This task, called multi-objective design space exploration, requires accurate strategies because the design space is too vast to be exhaustively evaluated. Even using efficient exploration strategies proposed in the literature, simulation times can become a bottleneck in the design flow. In this work we propose a novel approach to application-domain design space exploration using a multi-objective genetic algorithm and employing HPC to reduce exploration times. The genetic algorithm is preceded by a correlation analysis of the different objectives. The search space is thus reduced by combining highly correlated objectives from different domains. We describe the steps needed to parallelize the exploration on the grid, and present the results of extensive testing of the proposed approach. We obtained over one order of magnitude reduction in exploration times without hampering the quality of the solutions. Shorter simulation times allow more ideas to be explored in less time. This leads to shorter product time-to-market and a more thorough design space exploration. Furthermore the combination of correlated objectives favors the design of modern multi-purpose devices.