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This paper presents the design of an adiabatic/bootstrapped CMOS driver (xb-ad) using complementary pass-transistor logic (CPL) and a four-phase power clock. The proposed xb-ad uses a bootstrapped load driven circuit with PMOS and NMOS transistors driven by an NMOS evaluation logic block. When implemented on a 65 nm CMOS IV technology, under the large capacitive loading condition (16pF), xb-ad performs better than the reference adiabatic circuit (cpl-ad) in terms of active area (64%), and energy-delay product (39%). Moreover, xb-ad supports 10 times higher output capacitive load without any additional circuit sizing than cpl-ad.