With the advent of high-κ materials as a replacement to silicon oxynitride based gate dielectric, reliability study of high-κ (HK) based devices has become imperative. Processing of HK dielectrics is associated with a thin interfacial layer (IL) of SiOx sandwiched between the high-κ and silicon substrate making it a dual layer dielectric stack. We propose here a simple electrical test algorithm that enables successive separate breakdown and detection of each layer in the bilayer stack during accelerated time dependent dielectric breakdown testing. The algorithm uses the tunneling current mechanism as the yardstick to distinguish between HK and IL breakdown. This technique is useful to decode the Weibull slope of each of these layers in the dielectric stack and decipher their impact on the overall gate stack reliability.