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A high performance reconfigurable parallel processing architecture

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4 Author(s)
Shively, R.R. ; AT&TBell Laboratories, Whippany, New Jersey ; Morgan, E.B. ; Copley, T.W. ; Gorin, A.L.

The architecture of the AT&T DSP-3 parallel processor is described. The DSP-3 design is modular and when implemented with 128 processing nodes, provides a maximum throughput of 3.2 GFLOPS (32 bit floating point). The high speed interconnection network (40 Mbytes/sec) contains redundant paths that allow the machine to be configured in a variety of topologies. This flexibility supports efficient operation for a diverse set of signal processing applications and enables topology reconfiguration in support of fault tolerance. Advanced multi-chip 3-D packaging will allow a 800 MFLOP version of the machine to be realized in a multi-processor array volume of 9 cubic inches.

Published in:

Supercomputing, 1989. Supercomputing '89. Proceedings of the 1989 ACM/IEEE Conference on

Date of Conference:

12-17 Nov. 1989