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Current research into the problems of cache coherency in multiprocessor (MP) systems, has primarily focused on bus based memory interconnection networks (M-ICN) and the use of various types of “snooping” cache coherency protocols. Bus bandwidth limitations can be alleviated through the use of wider bandwidth general interconnection structures, such as a crossbar switch. However, if private caches are used, the cache coherency problem becomes multiply compounded. Little work has been done to address this problem. A new distributed shared-memory multiprocessor system with private caches and for use with general memory interconnection networks (M-ICNs) is presented. A new distributed cache coherency-controller ($-K) unit is employed to manage coherency invalidation/updating over a dedicated bus based coherency interconnection network (C-ICN). This allows for cache-to-cache coherency updating to reduce the M-ICN traffic to only that of instruction/data transactions. This architecture incorporates a unique hierarchical, preemptive cache coherency protocol, simple enough to be implemented in hardware. A feasible implementation of a fully asynchronous crossbar switch is also presented as a possible general memory interconnection network (M-ICN).