By Topic

C2MP: a cache-coherent, distributed memory multiprocessor-system

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Marquardt, D.E. ; Santa Clara University, Department of Electrical Engineering and Computer Science, Santa Clara, California ; Alkhatib, H.S.

Current research into the problems of cache coherency in multiprocessor (MP) systems, has primarily focused on bus based memory interconnection networks (M-ICN) and the use of various types of “snooping” cache coherency protocols. Bus bandwidth limitations can be alleviated through the use of wider bandwidth general interconnection structures, such as a crossbar switch. However, if private caches are used, the cache coherency problem becomes multiply compounded. Little work has been done to address this problem. A new distributed shared-memory multiprocessor system with private caches and for use with general memory interconnection networks (M-ICNs) is presented. A new distributed cache coherency-controller ($-K) unit is employed to manage coherency invalidation/updating over a dedicated bus based coherency interconnection network (C-ICN). This allows for cache-to-cache coherency updating to reduce the M-ICN traffic to only that of instruction/data transactions. This architecture incorporates a unique hierarchical, preemptive cache coherency protocol, simple enough to be implemented in hardware. A feasible implementation of a fully asynchronous crossbar switch is also presented as a possible general memory interconnection network (M-ICN).

Published in:

Supercomputing, 1989. Supercomputing '89. Proceedings of the 1989 ACM/IEEE Conference on

Date of Conference:

12-17 Nov. 1989