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Experimental validation of the NIOS II processor-FPGA on the digital control of PFC converter

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4 Author(s)
AndrĂ© L. P. Alcalde ; Federal University of Santa Catarina - Department of Electrical Engineering - Power Electronics Institute - INEP, P. O. BOX 5119 - 88040-970 - Florianópolis - SC - Brazil ; Hari B. Mohr ; Deivis Borgonovo ; Samir A. Mussa

This article discusses the application of the NIOS II processor in a PFC converter. This processor was provided by ALTERA to be implemented in FPGA. The FPGA is capable of a parallel processing and hardware modification, and also offers the possibility of microprocessor implementations, which can be programmed in Assembly or C. The NIOS II is a versatile embedded processor family that has a high performance and was created for FPGA. This processor family consists of three processor cores that implement a common instruction set architecture, each optimized for either a specific cost or performance, and all supported by the same software tools. The NIOS II Processor propitiates flexibility such as: selecting the exact set of CPUs, peripherals, and interfaces, accelerating only relevant functions and eliminating the risk of processor obsolescence. The focus of this paper is the use of this processor applied to the digital control of a single-phase pre-regulated rectifier, showing the advantages and disadvantages of the use of this technology. The control strategy used aims to obtain Power Factor Correction (PFC) of a single-phase voltage doubler rectifier with a center tap at the voltage output. The FPGA used in this study is an ALTERA Cyclone II EP2C35F672C6.

Published in:

2009 Brazilian Power Electronics Conference

Date of Conference:

Sept. 27 2009-Oct. 1 2009