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Asynchronous Combo 4/8/12bit, 140MS/s, 0.12mm2 ADC with binary tree structure

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4 Author(s)
Petrellis, N. ; Analogies S.A., Platani, Greece ; Birbas, M. ; Kikidis, J. ; Birbas, A.

A configurable asynchronous CMOS TSMC90 nm Analogue to Digital Converter (ADC) with 4, 8 or 12-bits resolution, using a binary tree structure is presented which needs very low silicon area and relatively low power consumption for its implementation. The sampling rate of the 12-bit ADC exceeds 140MS/s and requires only 0.12 mm2 of area making it appropriate for ultra wideband time-interleaved parallel ADC architectures.

Published in:

Emerging Technologies & Factory Automation, 2009. ETFA 2009. IEEE Conference on

Date of Conference:

22-25 Sept. 2009

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