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Efficient FPGA implementation of convolution

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2 Author(s)
Khader Mohammad ; Electrical and Computer Engineering Department, University of Texas at San Antonio, 1 UTSA Circle, San Antonio, TX 78249-0669 ; Sos Agaian

This paper presents a direct method of reducing convolution processing time using hardware computing and implementations of discrete linear convolution of two finite length sequences (NXN). This implementation method is realized by simplifying the convolution building blocks. The purpose of this research is to prove the feasibility of an application specific integrated circuit (ASIC) that performs a convolution on an acquired image in real time. The proposed implementation uses a modified hierarchical design approach, which efficiently and accurately speeds up computation; reduces power, hardware resources, and area significantly. The efficiency of the proposed convolution circuit is tested by embedding it in a top level FPGA. Simulation and comparison to different design approaches show that the circuit uses only 5 mw that saves almost 35% of area and is four times faster than what is implemented in. In addition, the presented circuit uses less power consumption and has a delay of 20 ns from input to output using 32 nm process library. It also provides the necessary modularity, expandability, and regularity to form different convolutions for any number of bits.

Published in:

Systems, Man and Cybernetics, 2009. SMC 2009. IEEE International Conference on

Date of Conference:

11-14 Oct. 2009