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Spare processor allocation for fault tolerance in torus-based multicomputers

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2 Author(s)
M. M. Bae ; Dept. of Comput. Sci., Oregon State Univ., Corvallis, OR, USA ; B. Bose

Some fault-tolerant architectures use the spare nodes or links to replace the faulty components. This paper gives solutions to spare processor placement problem for torus based networks. Optimal 1-hop spare processor placement methods for multi-dimensional tori and t-hop placement methods for 2D tori are described. In the presence of node failures, a system reconfiguration scheme using spare nodes is also given

Published in:

Fault Tolerant Computing, 1996., Proceedings of Annual Symposium on

Date of Conference:

25-27 Jun 1996