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Dynamic test compaction for synchronous sequential circuits using static compaction techniques

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2 Author(s)
I. Pomeranz ; Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA ; S. M. Reddy

Short test sequences for synchronous sequential circuits are important in reducing test application time and memory requirements. In addition, dynamic test compaction, where heuristics to generate short test sequences are incorporated into the test generation process, may also reduce test generation time. This is due to the fact that a smaller number of test vectors needs to be generated. We present a dynamic test compaction procedure. The compaction heuristics we use are based on previously proposed static compaction techniques. Conventionally, static compaction is applied as a postprocessing step, after the test sequence has been generated. In the proposed procedure, static compaction techniques are used while the test sequence is being generated, to reduce the need for postprocessing, or static compaction. Compared to other dynamic compaction procedures that generate very short test sequences, the computational overhead involved in the proposed procedure is significantly lower, yet short test sequences are obtained. The proposed techniques can be incorporated into other test generation procedures, to reduce the test lengths they produce

Published in:

Fault Tolerant Computing, 1996., Proceedings of Annual Symposium on

Date of Conference:

25-27 Jun 1996