Low-Temperature Formation of High-Quality $ \hbox{GeO}_{2}$ Interlayer for High-$\kappa$ Gate Dielectrics/Ge by Electron-Cyclotron-Resonance Plasma Techniques

We have fabricated an Al
₂
O
₃
/GeO
₂
gate-dielectric stack on p-type Ge by electron-cyclotron-resonance plasma oxidation and sputtering without external substrate heating. We show that the midgap interface state density at the GeO
₂
/Ge interface is 4.5 × 10
¹⁰
cm
^-2
· eV
^-1
. The hysteresis observed in capacitance-voltage measurements is reduced to 50 mV when the gate bias is swept from accumulation to inversion and back to accumulation or after a single dummy sweep from inversion to accumulation, indicating the possibility that the bulk oxide traps causing the hysteresis are deactivated by the injected holes. The band gap of GeO
₂
was determined by internal photoemission measurements to be 4.7 eV. The conduction- and valence-band offsets at the GeO
₂
/Ge interface are moderately symmetric and large with values of 1.8 and 2.2 eV, respectively. These promising results suggest that low-temperature plasma-grown GeO
₂
is a suitable interlayer between high-dielectric-constant dielectrics and Ge.