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SiO2/high-Â¿ dielectric stacks will soon replace the conventional SiO2-based dielectric stacks in flash memory cells, as the thickness of SiO2 -based stacks is approaching its fundamental limit. The electron trap density in high-Â¿ layers is orders of magnitude higher than that in SiO2, which may introduce excessive leakage via trap-assisted tunneling current and become the limiting factor for the retention of memory cells. Understanding the properties of electron traps throughout the dielectric stack is essential for estimating the leakage current and for selecting materials and processes in order to reduce the leakage. However, detailed information on trap properties in the bulk of high-Â¿ layers is still missing. A recently developed two-pulse C-V measurement technique is used in this paper to investigate the energy and spatial distribution of electron traps throughout the SiO2/Al2O3 dielectric stacks. Four energy regions of electron traps have been observed. The shallower traps mainly above the Si conduction band bottom E CB are found distributed across the Al2O3 layer. A narrow band of traps below Si E CB with a bandwidth of about 0.1 eV can be observed near the SiO2/Al2O3 interface. Traps in the midlevel region corresponding to Si bandgap and traps in the deeper energy region mainly below Si valence band top are also observed. The postdeposition annealing in N2 has different impacts on the electron traps in different energy regions.