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High Performance of Ge nMOSFETs Using \hbox {SiO}_{2} Interfacial Layer and TiLaO Gate Dielectric

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2 Author(s)
W. B. Chen ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Albert Chin

Using a SiO2 interfacial layer and a high-?? gate TiLaO dielectric, the TaN/TiLaO/SiO2 on Ge/Si nMOSFETs in this study showed a small 1.1-nm capacitance equivalent thickness, a good high field mobility of 201 cm2/(V ?? s) at 0.5 MV/cm, and a very low off-state leakage current of 3.5 ?? 10-10 A/??m. The self-aligned and gate-first metal-gate/high-?? and Ge nMOSFETs were processed using standard ion implantation and 550??C RTA. The proposed devices are fully compatible with current VLSI fabrication methods.

Published in:

IEEE Electron Device Letters  (Volume:31 ,  Issue: 1 )