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Power gating in circuits is one of the effective technologies to allow low leakage and high performance operations. The key design considerations in the power mode transitions of power gating technology are minimizing the wakeup delay (for achieving high performance), the peak current (for reducing power supply/ground noise), and the total size of sleep transistors (for reducing area/design complexity). This work aims to analyze and establish the relations between the three important design parameters: 1) the maximum current flowing from/to power/ground; 2) the wakeup (sleep to active mode transition) delay; and 3) the total size of sleep transistors. With the understanding of relations between the parameters, we propose solution to the problem of finding logic clusters and their wakeup schedule that minimize the wakeup delay while satisfying the peak current constraint in wakeup time and performance loss constraint in normal operation. Specifically, we solve the problem by formulating it into repeated (incremental) applications of finding a maximum clique in a graph. From the experiments using ISCAS benchmarks, it is shown that our proposed technique is able to explore the search space, finding solutions with 71% and 30% reduced sizes of sleep transistors and 39% and 54% reduced wakeup delay, compared to the results by the previous work.