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Digital circuits complexity and density are increasing while, at the same time, more quality and reliability are required. These trends, together with high test costs, make the validation of VLSI circuits more and more difficult. Beside high-end ATE machines, strictly necessary in ASIC production phase, low-cost ATE test systems take place into market to implement a valid support in ASIC development phase. In this paper a case study of low-cost, reconfigurable, versatile and easy-to-use FPGA-based test environment is presented. It allows patterns to be extracted from HDL-simulation and stimuli to be generated to ASIC prototypes, especially when a high-end test machine setup isn't foreseen or isn't available yet. This is the ideal solution for engineers to develop test programs and perform device tests and yield analysis on their desktop and then transfer the test program directly to production. The result is low-cost automatic test equipment, able to execute a preliminary digital test, using just a laptop and an FPGA-equipped board.
Date of Conference: 21-23 Sept. 2009