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A 12 bit 2.9 GS/s DAC With IM3  \ll - 60 dBc Beyond 1 GHz in 65 nm CMOS

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9 Author(s)

A 12 bit 2.9 GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an IM3 < ¿-60 dBc beyond 1 GHz while driving a 50 ¿ load with an output swing of 2.5 Vppd and dissipating a power of 188 mW. The SFDR measured at 2.9&nbsp; GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previously published results, is mainly obtained by adding local cascodes on top of the current-switches with ¿always-ON¿ biasing.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 12 )

Date of Publication:

Dec. 2009

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