Referenced Items are not available for this document.
This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1 m wireless link at 4 Gb/s QPSK with less than 10-11 BER.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:44
,
Issue:
12
)
Date of Publication: Dec. 2009
- Page(s):
- 3434 - 3447
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 11020456
- Digital Object Identifier :
- 10.1109/JSSC.2009.2032584
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 15 December 2009
- Issue Date :
- Dec. 2009
- Sponsored by :
- IEEE Solid-State Circuits Society
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