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A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery

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6 Author(s)
Yamaguchi, K. ; Device Platforms Res. Labs., NEC Corp., Sagamihara, Japan ; Hori, Y. ; Nakajima, K. ; Suzuki, K.
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A 2.0 Gb/s clock-embedded interface for LCD drivers, Advanced-PPmL¿, has been developed for high-speed data transfer and reduced area in transmission media. Only one pair of differential signals is needed to control the LCD driver and to display images. A newly developed 1/5-rate phase frequency detector helps achieve a 25% power reduction compared with a half-rate architecture. Pulse filtering of phase control signals and a 4B5B-based interface protocol have been developed for noise-tolerant clock recovery. Power consumption in the clock and data recovery (CDR) is 93 mW with a 3.0 V supply. The rms jitter in the recovered clock is 11 ps when a PRBS7 pattern is used.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 12 )