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A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time \Delta \Sigma ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 \mu m CMOS

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2 Author(s)
Park, M. ; Massachusetts Inst. of Technol., Cambridge, MA, USA ; Perrott, M.H.

The use of a VCO-based integrator and quantizer within a continuous-time (CT) ΔΣ analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 μm CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1.5 V supply and occupying an active area of 0.45 mm2 demonstrated. A key innovation is the explicit use of the oscillator's output phase to avoid the signal distortion that had severely limited the performance of earlier VCO-based ADCs, which had made use of its output frequency only. The proposed VCO-based integrator and quantizer structure enables fourth-order noise shaping with only three opamp-based integrators.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 12 )