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Low-Power High-Efficiency Class D Audio Power Amplifiers

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2 Author(s)
Miguel Angel Rojas-Gonzalez ; Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX, USA ; Edgar Sanchez-Sinencio

The architecture, design, and implementation of two clock-free analog class D audio power amplifiers using 0.5 ¿m CMOS standard technology are introduced. The amplifiers are designed to consume significantly less power than former implementations. Both designs operate with a 2.7 V single voltage supply and deliver a maximum output power of 250 mW into an 8 ¿ speaker. The two class-D amplifiers are based on a hysteretic sliding mode controller, which avoids the complex task of generating the highly linear triangle carrier signal used in conventional architectures. The first design generates a two-level modulated signal, known as binary modulated amplifier (BMA); the second topology implements a three-level modulated signal, also called ternary modulated amplifier (TMA). The architectures and implementations are simple and compact, providing very low quiescent power consumption. Experimental results of the BMA/TMA yield an efficiency of 89/90% and a total harmonic distortion plus noise (THD+N) of 0.02/0.03%, respectively. The efficiency and linearity is comparable to state-of-the-art amplifiers but the static power consumption is less than one tenth of previous proposed architectures. Both class D amplifiers achieve a power supply rejection ratio greater than 75 dB at 217 Hz, and a signal-to-noise ratio (SNR) higher than 90 dB within the whole audio band. Each amplifier occupies less than 1.5 mm2.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:44 ,  Issue: 12 )